A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization(VLSI Architecture,<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18μm 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8V, 25℃), a clock frequency of 266MHz can be achieved.

• 社団法人電子情報通信学会の論文
• 2006-12-01

著者

• GOTO Satoshi

  Graduate School of Information, Production and Systems, Waseda University

• Ikenaga Takeshi

  Graduate school of Information, Production and Systems, Waseda University

• Ikenaga Takeshi

  Graduate School Of Information Production And System Waseda University

• Ikenaga Takeshi

  Graduate School Of Ips Waseda University

• SONG Yang

  Graduate School of Information, Production and Systems, Waseda University

• Song Yang

  Graduate School Of Ips Waseda University

• Liu Zhenyu

  Kitakyushu Foundation For The Advancement Of Industry Science And Technology

• Liu Zhenyu

  Ips Waseda University

• Song Yang

  Graduate School Of Information Production And Systems Waseda University

• Goto Satoshi

  Graduate School Of Information Production And System Waseda University

• Liu Zhenyu

  Tsinghua University

• Ikenaga Takeshi

  The Graduate School Of Information Production And Systems Waseda University

• IKENAGA Takeshi

  Graduate School of Fundamental Science and Engineering, Waseda University

• Goto Satoshi

  Graduate School of Infomlation Production and Systems Waseda University

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