A High-Speed Design of Montgomery Multiplier
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概要
- 論文の詳細を見る
With the increase of key length used in public cryptographic algorithms such as RSA and ECC, the speed of Montgomery multiplication becomes a bottleneck. This paper proposes a high speed design of Montgomery multiplier. Firstly, a modified scalable high-radix Montgomery algorithm is proposed to reduce critical path. Secondly, a high-radix clock-saving dataflow is proposed to support high-radix operation and one clock cycle delay in dataflow. Finally, a hardware-reused architecture is proposed to reduce the hardware cost and a parallel radix-16 design of data path is proposed to accelerate the speed. By using HHNEC 0.25μm standard cell library, the implementation results show that the total cost of Montgomery multiplier is 130 KGates, the clock frequency is 180MHz and the throughput of 1024-bit RSA encryption is 352kbps. This design is suitable to be used in high speed RSA or ECC encryption/decryption. As a scalable design, it supports any key-length encryption/decryption up to the size of on-chip memory.
- （社）電子情報通信学会の論文
- 2008-04-01
著者
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GOTO Satoshi
IPS, Waseda University
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IKENAGA Takeshi
IPS, Waseda University
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Goto Satoshi
Waseda Univ. Jpn
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Ikenaga Takeshi
Graduate School Of Information Production And System Waseda University
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Ikenaga Takeshi
Graduate School Of Ips Waseda University
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Ikenaga Takeshi
Ips Waseda University
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Goto Satoshi
Ips Waseda University
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IKENAGA Takeshi
The Graduate School of Information, Production and Systems, Waseda University
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FAN Yibo
IPS, Waseda University
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Fan Yibo
Ips Waseda University
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