Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC
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概要
- 論文の詳細を見る
Integer Motion Estimation (IME) costs much computation in H.264/AVC video encoder. 2-D SAD tree IME architecture provides very high performance for encoder, and it has been used by many video codec designs. This paper proposes an optimized hardware design of 2-D SAD tree IME. Firstly, a new hardware architecture is proposed to reduce on-chip memory size. Secondly, a new search pattern is proposed to fully use memory bandwidth and reduce external memory access. Thirdly, the data-path is redesigned, and the performance is greatly improved. In order to compare with other IME designs, an IME design support D1 size, 30fps with search range [±32, ±32] is implemented. The hardware cost of this design includes 118 KGates and 8Kb SRAM, the maximum clock frequency is 200MHz. Compared to the original 2-D SAD tree IME, our design saves 87.5% on-chip memory, and achieves 3 times performance than original one. Our design provides a new way to design a low cost and high performance IME for H.264/AVC encoder.
- 2011-04-01
著者
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GOTO Satoshi
IPS, Waseda University
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Zeng Xiaoyang
State Key Lab. Of Asic & System Fudan University
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FAN Yibo
State Key Lab. of ASIC & System, Fudan University
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Fan Yibo
State Key Lab. Of Asic & System Fudan University
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Fan Yibo
State Key Lab Of Asic And System Fudan University
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Zeng Xiaoyang
State Key Lab Of Asic And System Fudan University
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ZENG Xiaoyang
State Key Lab of ASIC & System, Fudan University
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