Ikenaga Takeshi | Waseda Univ.

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概要

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著作論文

BS-12-19 A Fast Block Type Decision Algorithm for H.264/AVC Intra Prediction(BS-12. Network Planning, Control, and Management)
D-11-14 A Mode Reduction Based Fast Integer Motion Estimation Algorithm for HDTV
Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms(VLSI Architecture for Communication/Server Systems,VLSI Technology toward Frontiers of New Market)
Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule(VLSI Architecture,VLSI Design and CAD Algorithms)
Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving(Adaptive Signal Processing, Recent Advances in Circuits and Systems-Part 1)
BS-12-18 A Novel Hardware-Friendly Regular 3-Step Integer Motion Estimation Algorithm for H.264/AVC(BS-12. Network Planning, Control, and Management)
D-11-18 An Edge Information Based Block Size Decision Method for Intra Mode Decision in H.264/AVC
D-11-19 Multi-Stage Based Inter Mode Decision Algorithm in H.264/AVC
D-11-21 Macroblock Level Rate Control for H.264/AVC Based on Model Parameter Update and Weighted Reference Calculation
D-11-20 Bayesian Decision Based All-Zero Block Detection Algorithm in H.264/AVC
A-4-15 Cross Low Pass Filter Based Subsampling Algorithm for H.264/AVC Motion Estimation
BS-12-20 VLSI Design of Level C Bandwidth Reduction Scheme for MPEG-2 to H.264/AVC Transcoding(BS-12. Network Planning, Control, and Management)
Content-Based Motion Estimation with Extended Temporal-Spatial Analysis(Image Processing and Multimedia Systems, Recent Advances in Circuits and Systems-Part 1)
Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique
A 41mW VGA【triple bond】fps Quadtree Video Encoder for Video Surveillance Systems
Standard Deviation and Intra Prediction Mode Based Adaptive Spatial Error Concealment (SEC) in H.264/AVC
Variable Block Size Motion Vector Retrieval Schemes for H.264 Inter Frame Error Concealment
High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding
Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application
Hardware-Oriented Early Detection Algorithms for 4×4 and 8×8 All-Zero Blocks in H.264
VLSI Oriented Fast Motion Estimation Algorithm Based on Pixel Difference, Block Overlapping and Motion Feature Analysis
Macroblock Feature Based Complexity Reduction for H.264/AVC Motion Estimation
Macroblock and Motion Feature Analysis to H.264/AVC Fast Inter Mode Decision
Content-Aware Fast Motion Estimation for H.264/AVC
Edge Block Detection and Motion Vector Information Based Fast VBSME Algorithm
A-4-18 Integer Search Position Based Fast Motion Estimation in H.264/AVC
Constant Bit-Rate Multi-Stage Rate Control for Rate-Distortion Optimized H.264/AVC Encoders
A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing Schedule
A-4-33 High Throughput Rate-1/2 Partially-Parallel Irregular LDPC Decoder
An Ultra-Low Bandwidth Design Method for MPEG-2 to H.264/AVC Transcoding

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