Zhou Dajiang | Graduate School Of Information Production And Systems Waseda University
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- 同名の論文著者
- Graduate School Of Information Production And Systems Waseda Universityの論文著者
関連著者
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Zhou Dajiang
Graduate School Of Information Production And Systems Waseda University
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Goto Satoshi
Graduate School Of Information Production And System Waseda University
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Goto Satoshi
Graduate School of Infomlation Production and Systems Waseda University
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GOTO Satoshi
Graduate School of Information, Production and Systems, Waseda University
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Goto Satoshi
Waseda Univ. Jpn
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Zhou Dajiang
Waseda Univ. Kitakyushu‐shi Jpn
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GOTO Satoshi
Waseda University
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Zhao Xiongxin
Graduate School Of Information Production And Systems Waseda University
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Chen Zhixiang
Graduate School Of Information Production And Systems Waseda University
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Peng Xiao
Graduate School Of Information Production And Systems Waseda University
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Zhou Jinjia
Graduate School Of Information Production And Systems Waseda University
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Zhu Jiayi
Department Of Electronic Engineering Shanghai Jiao Tong University
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CHEN Zhixiang
Graduate School of Information, Production and Systems, Waseda University
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Peng Xiao
Waseda Univ. Kitakyushu‐shi Jpn
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Zhao Xiongxin
Waseda Univ. Kitakyushu‐shi Jpn
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Chen Zhixiang
Waseda Univ. Kitakyushu‐shi Jpn
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Xiongxin Zhao
School of Information, Production and Systems, Waseda University
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PENG Xiao
Graduate School of Information, Production and Systems, Waseda University
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ZHAO Xiongxin
Graduate School of Information, Production and Systems, Waseda University
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ZHOU Jinjia
Graduate School of Information, Production and Systems, Waseda University
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Goto Satoshi
Graduate School Of Information Production And Systems Waseda University
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Zhou Dajiang
Ips Waseda University
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ZHU Jiayi
Department of Electronic Engineering, Shanghai Jiao Tong University
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HE Xun
Graduate School of Information, Production and Systems, Waseda University
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He Xun
Graduate School Of Information Production And Systems Waseda University
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HE Gang
Graduate School of Information, Production and Systems, Waseda University
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He Gang
Graduate School Of Information Production And Systems Waseda University
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GOTO Satoshi
IPS, Waseda University
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Zhang Tianruo
Graduate school of Information, Production and Systems, Waseda University
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CHEN Xianmin
Department of Electronic Engineering, Shanghai Jiao Tong University
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LIU Peilin
Department of Electronic Engineering, Shanghai Jiao Tong University
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ZHOU Dajiang
IPS, Waseda University
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PAN Xingguang
Department of Electronic Engineering, Shanghai Jiao Tong University
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Zhang Tianruo
Graduate School Of Information Production And System Waseda University
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Jin Xin
Graduate School Of Information Production And System Waseda University
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Liu Peilin
Department Of Electronic Engineering Shanghai Jiao Tong University
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Chen Xianmin
Department Of Electronic Engineering Shanghai Jiao Tong University
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Wang Minghui
Graduate School Of Information Production And System Waseda University
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Pan Xingguang
Department Of Electronic Engineering Shanghai Jiao Tong University
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Jin Xin
Information Technology Research Organization Waseda University
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Zhang Tianruo
Graduate School Of Information Production And Systems Waseda University
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Okamura Leona
Graduate School Of Information Production And System Waseda University
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Zhou Dajiang
Graduate School of Information, Production and Systems, Waseda University
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LI Muchen
Graduate School of Information, Production and Systems, Waseda University
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PENG Xiao
NEC Corporation
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Li Guo
Graduate School of Information Production and Systems Waseda University Japan
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Pan Yue
Graduate School of Information Production and Systems Waseda University
著作論文
- A LOW-POWER AND PERFORMANCE-AWARE DVB-S2 LDPC DECODER WITH LAYERED SCHEDULING
- A high-parallelism reconfigurable permutation network for IEEE 802.11n/803.16e LDPC decoder (情報理論)
- An Efficient Motion Vector Coding Scheme Based on Prioritized Reference Decision
- A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder
- A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications
- A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
- A 530Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder
- Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder
- A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS
- A 98GMACs/W 32-Core Vector Processor in 65nm CMOS
- A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip
- A 115mW 1Gbps Bit-Serial Layered LDPC Decoder for WiMAX
- A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS
- A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC
- A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS
- D-11-62 An Efficient Lossless Reference Frame Recompression Scheme
- D-11-67 Interface Design for FPGA-based Video Decoder