Zhu Jiayi | Department Of Electronic Engineering Shanghai Jiao Tong University
スポンサーリンク
概要
関連著者
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GOTO Satoshi
Graduate School of Information, Production and Systems, Waseda University
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Goto Satoshi
Waseda Univ. Jpn
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Zhou Dajiang
Waseda Univ. Kitakyushu‐shi Jpn
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Zhou Dajiang
Graduate School Of Information Production And Systems Waseda University
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Zhu Jiayi
Department Of Electronic Engineering Shanghai Jiao Tong University
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Zhou Jinjia
Graduate School Of Information Production And Systems Waseda University
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GOTO Satoshi
Waseda University
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Goto Satoshi
Graduate School Of Information Production And System Waseda University
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Goto Satoshi
Graduate School of Infomlation Production and Systems Waseda University
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ZHOU Jinjia
Graduate School of Information, Production and Systems, Waseda University
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Zhou Dajiang
Ips Waseda University
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ZHU Jiayi
Department of Electronic Engineering, Shanghai Jiao Tong University
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HE Gang
Graduate School of Information, Production and Systems, Waseda University
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He Gang
Graduate School Of Information Production And Systems Waseda University
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GOTO Satoshi
IPS, Waseda University
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Zhang Tianruo
Graduate school of Information, Production and Systems, Waseda University
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CHEN Xianmin
Department of Electronic Engineering, Shanghai Jiao Tong University
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LIU Peilin
Department of Electronic Engineering, Shanghai Jiao Tong University
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ZHOU Dajiang
IPS, Waseda University
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PAN Xingguang
Department of Electronic Engineering, Shanghai Jiao Tong University
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Zhang Tianruo
Graduate School Of Information Production And System Waseda University
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Liu Peilin
Department Of Electronic Engineering Shanghai Jiao Tong University
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Chen Xianmin
Department Of Electronic Engineering Shanghai Jiao Tong University
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Pan Xingguang
Department Of Electronic Engineering Shanghai Jiao Tong University
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HE Xun
Graduate School of Information, Production and Systems, Waseda University
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He Xun
Graduate School Of Information Production And Systems Waseda University
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Zhang Tianruo
Graduate School Of Information Production And Systems Waseda University
著作論文
- An Efficient Motion Vector Coding Scheme Based on Prioritized Reference Decision
- A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder
- A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications
- A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
- A 530Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder
- Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder