Zhou Dajiang | Waseda Univ. Kitakyushu‐shi Jpn
スポンサーリンク
概要
関連著者
-
Zhou Dajiang
Waseda Univ. Kitakyushu‐shi Jpn
-
GOTO Satoshi
Graduate School of Information, Production and Systems, Waseda University
-
Goto Satoshi
Waseda Univ. Jpn
-
Zhou Dajiang
Graduate School Of Information Production And Systems Waseda University
-
Goto Satoshi
Graduate School Of Information Production And System Waseda University
-
GOTO Satoshi
Waseda University
-
Goto Satoshi
Graduate School of Infomlation Production and Systems Waseda University
-
Peng Xiao
Waseda Univ. Kitakyushu‐shi Jpn
-
Zhao Xiongxin
Waseda Univ. Kitakyushu‐shi Jpn
-
Chen Zhixiang
Waseda Univ. Kitakyushu‐shi Jpn
-
Zhu Jiayi
Department Of Electronic Engineering Shanghai Jiao Tong University
-
Zhou Jinjia
Graduate School Of Information Production And Systems Waseda University
-
CHEN Zhixiang
Graduate School of Information, Production and Systems, Waseda University
-
Zhao Xiongxin
Graduate School Of Information Production And Systems Waseda University
-
Chen Zhixiang
Graduate School Of Information Production And Systems Waseda University
-
Peng Xiao
Graduate School Of Information Production And Systems Waseda University
-
Xiongxin Zhao
School of Information, Production and Systems, Waseda University
-
ZHOU Jinjia
Graduate School of Information, Production and Systems, Waseda University
-
Goto Satoshi
Waseda Univ.
-
PENG Xiao
Graduate School of Information, Production and Systems, Waseda University
-
ZHAO Xiongxin
Graduate School of Information, Production and Systems, Waseda University
-
Goto Satoshi
Graduate School Of Information Production And Systems Waseda University
-
Zhou Dajiang
Ips Waseda University
-
ZHU Jiayi
Department of Electronic Engineering, Shanghai Jiao Tong University
-
HE Xun
Graduate School of Information, Production and Systems, Waseda University
-
He Xun
Graduate School Of Information Production And Systems Waseda University
-
HE Gang
Graduate School of Information, Production and Systems, Waseda University
-
He Gang
Graduate School Of Information Production And Systems Waseda University
-
Zhao Xiongxin
Waseda University
-
GOTO Satoshi
IPS, Waseda University
-
Zhang Tianruo
Graduate school of Information, Production and Systems, Waseda University
-
CHEN Xianmin
Department of Electronic Engineering, Shanghai Jiao Tong University
-
LIU Peilin
Department of Electronic Engineering, Shanghai Jiao Tong University
-
ZHOU Dajiang
IPS, Waseda University
-
PAN Xingguang
Department of Electronic Engineering, Shanghai Jiao Tong University
-
Zhang Tianruo
Graduate School Of Information Production And System Waseda University
-
Jin Xin
Graduate School Of Information Production And System Waseda University
-
Liu Peilin
Department Of Electronic Engineering Shanghai Jiao Tong University
-
Chen Xianmin
Department Of Electronic Engineering Shanghai Jiao Tong University
-
Wang Minghui
Graduate School Of Information Production And System Waseda University
-
Pan Xingguang
Department Of Electronic Engineering Shanghai Jiao Tong University
-
Jin Xin
Information Technology Research Organization Waseda University
-
Zhang Tianruo
Graduate School Of Information Production And Systems Waseda University
-
Okamura Leona
Graduate School Of Information Production And System Waseda University
-
Chen Zhixiang
Waseda University
-
Peng Xiao
Waseda University
-
Zhou Dajiang
Waseda University
-
ZHU Jiayi
Waseda University
著作論文
- A LOW-POWER AND PERFORMANCE-AWARE DVB-S2 LDPC DECODER WITH LAYERED SCHEDULING
- A high-parallelism reconfigurable permutation network for IEEE 802.11n/803.16e LDPC decoder (情報理論)
- An Efficient Motion Vector Coding Scheme Based on Prioritized Reference Decision
- A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder
- A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications
- A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
- A 530Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder
- Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder
- A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS
- A 98GMACs/W 32-Core Vector Processor in 65nm CMOS
- A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip
- DVB-T2 LDPC Decoder with Perfect Conflict Resolution
- DVB-T2 LDPC Decoder with Perfect Conflict Resolution
- A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder