Okamura Leona | Graduate School Of Information Production And System Waseda University
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概要
- OKAMURA Leonaの詳細を見る
- 同名の論文著者
- Graduate School Of Information Production And System Waseda Universityの論文著者
関連著者
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Okamura Leona
Graduate School Of Information Production And System Waseda University
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Yoshihara Tsutomu
Graduate School Of Information Production And System Waseda University
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CHEN Zhixiang
Graduate School of Information, Production and Systems, Waseda University
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GOTO Satoshi
Graduate School of Information, Production and Systems, Waseda University
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GOTO Satoshi
Waseda University
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Goto Satoshi
Waseda Univ. Jpn
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Peng Xiao
Waseda Univ. Kitakyushu‐shi Jpn
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Zhou Dajiang
Waseda Univ. Kitakyushu‐shi Jpn
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Zhao Xiongxin
Waseda Univ. Kitakyushu‐shi Jpn
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Chen Zhixiang
Waseda Univ. Kitakyushu‐shi Jpn
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Zhou Dajiang
Graduate School Of Information Production And Systems Waseda University
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Zhao Xiongxin
Graduate School Of Information Production And Systems Waseda University
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Chen Zhixiang
Graduate School Of Information Production And Systems Waseda University
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Peng Xiao
Graduate School Of Information Production And Systems Waseda University
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Goto Satoshi
Graduate School Of Information Production And System Waseda University
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Yoshihara Tsutomu
Graduate School Of Information Production And Systems Waseda University
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Okamura Leona
Graduate School Of Information Production And Systems Waseda University
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ZHANG Yimeng
Graduate School of Information, Production and Systems, Waseda University
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Zhang Yimeng
Graduate School Of Information Production And System Waseda University
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Zhang Yimeng
Graduate School Of Information Production And Systems Waseda University
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HUANG Mengshu
Graduate School of Information, Production and System, Waseda University
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Huang Mengshu
Graduate School Of Information Production And System Waseda University
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Xiongxin Zhao
School of Information, Production and Systems, Waseda University
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Goto Satoshi
Graduate School of Infomlation Production and Systems Waseda University
著作論文
- An Energy Efficiency 4-bit Multiplier with Two-Phase Non-overlap Clock Driven Charge Recovery Logic
- An Area Efficiency Hybrid Decoupling Scheme for Charge Pump Noise Suppression in Non-volatile Memory
- A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip