D-11-67 Interface Design for FPGA-based Video Decoder
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概要
- 論文の詳細を見る
An FPGA design of 1080p H.264 video decoder is proposed in this paper. The design focuses on the interfaces between the decoder engine and the FPGA system. Besides, reading encoded data and displaying decoded video on a 1080p display are also included in our design. In this paper, the overall scheme and some key designs are described. Finally, the performance of the design is reported.
- 2013-03-05
著者
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Zhou Dajiang
Graduate School Of Information Production And Systems Waseda University
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Goto Satoshi
Graduate School of Infomlation Production and Systems Waseda University
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Pan Yue
Graduate School of Information Production and Systems Waseda University
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