A-3-4 Research on 3D LSI Multimedia Processing Chip
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概要
- 論文の詳細を見る
- 一般社団法人電子情報通信学会の論文
- 2013-03-05
著者
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Goto Satoshi
Graduate School of Information Production and Systems Waseda University Japan
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Goto Satoshi
Graduate School of Infomlation Production and Systems Waseda University
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Zhou Daj
Graduate School of Information Production and Systems Waseda University Japan
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Nan Duan
Graduate School of Information Production and Systems Waseda University Japan
関連論文
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- D-11-50 A Novel Fast Block Type Decision Algorithm for Intra Prediction in H.264/AVC High Profile
- A-16-2 A Fast Mode Decision Algorithm for H.264/AVC Intra Prediction
- A LOW-POWER AND PERFORMANCE-AWARE DVB-S2 LDPC DECODER WITH LAYERED SCHEDULING
- Region-of-Interest based Preprocessing for H.264/AVC Encoding
- A Macroblock Homogeneity Detection Method and its Application for Block Size Decision in H.264/AVC
- Fast Inter Mode Decision Algorithm Based on Residual Feature
- Turbo decoding based on LDPC message passing algorithm
- Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms(VLSI Architecture for Communication/Server Systems,VLSI Technology toward Frontiers of New Market)
- Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule(VLSI Architecture,VLSI Design and CAD Algorithms)
- Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving(Adaptive Signal Processing, Recent Advances in Circuits and Systems-Part 1)
- A-16-11 Level C+ Bandwidth Reduction Method for MPEG-2 to H.264 Transcoding
- A-16-1 Group-Based Prediction Scheme on Multiple Reference Frame Fractional Motion Estimation in H.264/AVC
- D-11-70 Adaptive Spatial EC based on Numerical Measures of Edge Statistical Model
- An adaptive error concealment order in H.264/AVC (VLSI設計技術)
- An adaptive error concealment order in H.264/AVC (集積回路)
- A-4-15 Cross Low Pass Filter Based Subsampling Algorithm for H.264/AVC Motion Estimation
- BS-12-20 VLSI Design of Level C Bandwidth Reduction Scheme for MPEG-2 to H.264/AVC Transcoding(BS-12. Network Planning, Control, and Management)
- Lossy Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations(Advanced Image Technology)
- A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization(VLSI Architecture,VLSI Design and CAD Algorithms)
- Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
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- Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique
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- A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications
- D-11-17 MOTION CORRELATION ADAPTION BASED INTER MODE DECISION ALGORITHM FOR H.264/AVC
- A High Throughput LDPC Decoder Design Based on Novel Delta-value Message-passing Schedule
- A Selective Video Encryption Scheme for MPEG Compression Standard(Application, Cryptography and Information Security)
- Adaptive Search Range Algorithms for Variable Block Size Motion Estimation in H.264/AVC
- Content-Aware Fast Motion Estimation for H.264/AVC
- Periodic Spectrum Transmission for Single-Carrier Transmission Frequency-Domain Equalization(Wireless Communication Technologies)
- A-5-34 Closed Form Expression for Bit Error Rate Performance of UWB Signal in the Presence of Inter-Symbol Interference
- A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing Schedule
- D-11-15 A Novel Three-Step Error Concealment Method for H.264/AVC
- A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
- An Ultra-Low Bandwidth Design Method for MPEG-2 to H.264/AVC Transcoding
- Voltage and Level-Shifter Assignment Driven Floorplanning
- A-6-12 Prediction-based Center-bias Fast Fractional Motion Estimation Algorithm for H.264/AVC
- Histogram of Template for Pedestrian Detection
- Generic Permutation Network for QC-LDPC Decoder
- D-11-20 An Adaptive Reference Frame Compression Scheme for Video Decoding
- ROI based Computational Complexity Reduction Scheme for H.264/AVC Encoder
- Scale invariance based salient contour detection (「膨大化する画像データのための高度画像入出力技術」[画像電子]学会創立35周年記念論文特集号)
- Fast Methods to Estimate Clock Jitter due to Power Supply Noise(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- Low bit rate overhead based reference modification for error resilient video coding
- Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining
- A 530Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder
- Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder
- A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS
- A 98GMACs/W 32-Core Vector Processor in 65nm CMOS
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- A 115mW 1Gbps Bit-Serial Layered LDPC Decoder for WiMAX
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- Content Adaptive Hierarchical Decision of Variable Coding Block Sizes in High Efficiency Video Coding for High Resolution Videos
- All-Zero Block-Based Optimization for Quadtree-Structured Prediction and Residual Encoding in High Efficiency Video Coding
- An Integrated Hole-Filling Algorithm for View Synthesis
- A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC
- Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips
- Correlated Noise Reduction for Electromagnetic Analysis
- A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS
- A-7-6 Dual Integrity Verification in OTP-based Security Chip
- A-3-4 Research on 3D LSI Multimedia Processing Chip
- D-11-67 Interface Design for FPGA-based Video Decoder
- D-11-53 An HEVC CU Pruning Method based on Depth