Channel Length Scaling and Surface Nitridation of Silicon Nanocrystals for High-Performance Electron Devices
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概要
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Silicon nanocrystal (SiNC)-based thin-film devices have been fabricated, where the idea of scaling down of channel length was implemented in such a way that very few SiNCs can be fitted inside the channel in the channel length direction in order to decrease the number of barriers to increase electrical conductivity. In this study, we have demonstrated the scaling down of channel length to 20 nm in order to reduce the number of barriers provided by each of the SiNCs, which are fabricated using a very high-frequency (VHF) plasma-enhanced chemical vapor deposition (CVD) system with a diameter of 10\pm 1 nm. A high electrical conductivity has been achieved by optimizing channel length. In addition, we have demonstrated the surface nitridation of SiNCs to protect the highly reactive surface of SiNCs from further natural oxidization and successfully suppressed the degradation of transport properties.
- 2013-04-25
著者
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Kodera Tetsuo
Quantum Nanoelectronics Research Center (QNERC), Tokyo Institute of Technology, Meguro, Tokyo 152-8550, Japan
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Usami Koichi
Quantum Nanoelectronics Research Center (QNERC), Tokyo Institute of Technology, Meguro, Tokyo 152-8550, Japan
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Nakamine Yoshifumi
Quantum Nanoelectronics Research Center, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro-ku, Tokyo 152-8552, Japan
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Oda Shunri
Quantum Nanoelectronics Research Center (QNERC), Tokyo Institute of Technology, Meguro, Tokyo 152-8550, Japan
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Usami Koichi
Quantum Nanoelectronics Research Center and Department of Physical Electronics, Tokyo Institute of Technology, Meguro, Tokyo 152-8852, Japan
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Ferdous Susoma
Quantum Nanoelectronics Research Center and Department of Physical Electronics, Tokyo Institute of Technology, Meguro, Tokyo 152-8852, Japan
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Kawano Yukio
Quantum Nanoelectronics Research Center and Department of Physical Electronics, Tokyo Institute of Technology, Meguro, Tokyo 152-8852, Japan
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