Self-Heating Effects and Analog Performance Optimization of Fin-Type Field-Effect Transistors
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概要
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The self-heating effects (SHEs) of bulk and silicon-on-insulator (SOI) fin-type field-effect transistors (FinFETs) and their impacts on circuit performance have been investigated on the basis of a realistic thermal conductivity of silicon. The heat dissipation via interconnect wires and interface thermal resistance in the high-\kappa gate stack were incorporated in simulations. It is shown that the depth of the shallow trench isolation (STI) of bulk FinFETs cannot be decreased to less than 100 nm owing to the increase in off-state leakage current. We observed that the thermal resistance R_{\text{th}} of SOI FinFETs greatly decreases upon thinning the buried oxide (BOX) layer. When the BOX thickness t_{\text{BOX}} is less than 50 nm, the R_{\text{th}} of SOI FinFETs is smaller than that of bulk FinFETs with an STI thickness of 100 nm, indicating a lower operation temperature of the thin-BOX SOI FinFETs than that of bulk FinFETs. The lower operation temperature of the 5-nm BOX SOI FinFET was confirmed under a practical bias condition for analog operations. In fin width, W_{\scale70%\tbox{fin}}, versus R_{\text{th}} characteristics, a strong W_{\scale70%\tbox{fin}} dependence of R_{\text{th}} was observed only in the bulk FinFETs, implying that fluctuations in W_{\scale70%\tbox{fin}} result in the variability of the operation temperature of the bulk FinFETs. Analog performance has been analyzed by calculating the cutoff frequency f_{\text{T}} and the maximum oscillation frequency f_{\text{max}}. We demonstrated that both f_{\text{T}} and f_{\text{max}} can be maximized in SOI FinFETs by optimizing t_{\text{BOX}} with regard to electrical and thermal properties. Better analog performance, and hence the optimization of t_{\text{BOX}}, are indispensable for the device design of a FinFET-based system-on-a-chip (SoC) platform.
- 2013-04-25
著者
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Uchida Ken
Department Of Biology Faculty Of Science Kumamoto University
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Oda Shunri
Quantum Nanoelectronics Research Center (QNERC), Tokyo Institute of Technology, Meguro, Tokyo 152-8550, Japan
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Takahashi Tsunaki
Department of Physical Electronics, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan
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Beppu Nobuyasu
Department of Physical Electronics, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan
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Chen Kunro
Department of Physical Electronics, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan
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