Design of 1024-l/Os 3.84GB/s High Bandwidth 600mW Low Power 16Mb DRAM Macros for Parallel Image Processing RAM(Special Issue on Multimedia, Network, and DRAM LSIs)

概要

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We have developed a parallel image processing RAM (PIP-RAM) which integrates a 16-Mb DRAM and 128 processor elements (PEs) by means of 0.38-μm CMOS 64-Mb DRAM process technology. It achieves 7.68-GIPS processing performance and 3.84-GB/s memory bandwidth with only l-W power dissipation (@ 30-MHz), and the key to this performance is the DRAM design. This paper presents the key circuit techniques employed in the DRAM design : 1) a paged-segmentation accessing scheme that reduces sense amplifier power dissipation, and 2) a clocked low-voltage-swing differential-charge-transfer scheme that reduces data line power dissipation with the help of a multi-phase synchronization DRAM control scheme. These techniques have general importance for the design of LSIs in which DRAMs and logic are tightly integrated on single chips.
社団法人電子情報通信学会の論文
1998-05-25