High-Speed High-Density Self-Aligned PNP Technology for Low-Power Complementary Bipolar ULSIs

概要

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A high-speed high-density self-aligned pnp technology for complementary bipolar ULSIs has been developed to achieve high-speed and low-power performance simultaneously. It is fully compatible with the npn process. A low sheet-resistance p^+ buried layer and a low sheet-resistance extrinsic n^+ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20μm^2. Current gain of 85 with 4-V collector-emitter breakdown voltage was obtained without any leakage current arising from emitter-base forward tunneling or recombination, which indicates no extrinsic base encroachment problem. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm, obtained by utilizing an optimized retrograded p-well, an arsenic-implanted intrinsic base, and emitter diffusion from BF_2-implanted polysilicon, improve the maximum cutoff frequency to 35 GHz. The power dissipation of the pnp pull-down complementary emitter-follower ECL circuit with load capacitances is calculated to be reduced to 20-40% of a conventional ECL circuit.
社団法人電子情報通信学会の論文
1995-04-25