Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally(Special Section on Papers Selected from ITC-CSCC 2001)

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概要

• 論文の詳細を見る

• A new four-quadrant (4Q) Multiplier complementally using linear and saturation regions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is proposed for the wide dynamic range and superior flexibility of the input range. This multiplier operates in the region except for the threshold voltage V_T to zero. The validity of the proposed circuit is confirmed through HSPICE simulation.

• 社団法人電子情報通信学会の論文
• 2002-06-01

著者

• ASAI Hideki

  Dept. of Systems Eng., Shizuoka University

• Asai H

  Shizuoka Univ. Hamamatsu‐shi Jpn

• Asai Hideki

  Department Of Systems Engineering Faculty Of Engineering Shizuoka University

• Asai Hideki

  Shizuoka Univ. Hamamatsu‐shi Jpn

• SUZUKI Tsutomu

  Department of Applied and Environmental Chemistry, Kitami Institute of Technology

• Asai Hideki

  Department Of Opto-electronics&mechanical Engineering Faculty Of Engineering Shizuoka University

• YONEYAMA Teru

  Department of Systems Engineering, Faculty of Engineering, Shizuoka University

• OURA Takao

  Department of System Engineering,Faculty of Engineering,Shizuoka University

• YONEYAMA Teru

  System LSI Division,NEC Electronics

• Yoneyama Teru

  System Lsi Division Nec Electronics

• Oura Takao

  Department Of System Engineering Faculty Of Engineering Shizuoka University

• Asai Hideki

  Department Of Applied Chemistry Faculty Of Engineering Okayama University

• Suzuki Tsutomu

  Department Of Systems Engineering Faculty Of Engineering Shizuoka University

• Suzuki Tsutomu

  Department Of Applied And Environmental Chemistry Kitami Institute Of Technology

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