ASAI Hideki | Dept. of Systems Eng., Shizuoka University

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概要

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著作論文

An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit
An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit
Matrix Order Reduction by Nodal Analysis Formulation and Relaxation-Based Fast Simulation for Power/Ground Plane
CMOS Circuit Simulation Using Latency Insertion Method
Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog Algorithm(Analog Circuit Techniques and Related Topics)
An Enhanced Time-Domain Circuit Simulation Technique Based on LIM(Numerical Analysis and Optimization)
An Efficient Simulation Method of Linear/Nonlinear Mixed Circuits Based on Hybrid Model Order Reduction Technique(Nonlinear Theory and its Applications)
An Efficient Simulator for Multiport Interconnects with Model Order Reduction Technique(Special Section on Papers Selected from ITC-CSCC 2001)
A New Methodology for Optimal Placement of Decoupling Capacitors on Printed Circuit Board
Transient Analysis for Transmission Line Networks Using Expanded GMC (Special Section on Nonlinear Theory and Its Applications)
Relaxation-Based Transient Analysis of Lossy Coupled Transmission Lines Circuits Using Delay Evaluation Technique(Special Section of Papers Selected from ITC-CSCC'97)
Design Method of Neural Networks for Limit Cycle Generator by Linear Programming
A Fast Neural Network Simulator for State Transition Analysis (Special Section on Nonlinear Theory and Its Applications)
A Fast Algorithm for Spatiotemporal Pattern Analysis of Neural Networks with Multivalued Logic (Special Section on Nonlinear Theory and Its Applications)
A Neuro-Based Optimization Algorithm for Rectangular Puzzles(Special Section of Papers Selected from ITC-CSCC'97)
New Criteria of Selective Orthogonal Matrix Least-Squares Method for Macromodeling Multiport Networks Characterized by Sampled Data(Analog Circuit Techniques and Related Topics)
A Low Voltage Floating Resistor Circuit Having Both Positive and Negative Resistance Values
Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally(Special Section on Papers Selected from ITC-CSCC 2001)
A Structure to realize various kinds of floating resistors
A CMOS Floating Resistor Circuit Having Both Positive and Negative Resistance Values(Special Section on Analog Circuit Techniques and Relate)
A Positive Negative Resistor for Synaptic Weights
A Positive Floating Resistor and A Negative Floating Resistor for the Analog Neural Network Implementation
An Approach for Practical Use of Common-Mode Noise Reduction Technique for In-Vehicle Electronic Equipment

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