A CMOS Floating Resistor Circuit Having Both Positive and Negative Resistance Values(<特集>Special Section on Analog Circuit Techniques and Relate)
スポンサーリンク
概要
- 論文の詳細を見る
In this report, we propose a new bilateral floating resistor circuit having both positive and negative resistance values. The equivalent resistance of this floating resistor in CMOS technology can be changed by using controlled-voltages, which is an advantage over polysilicon or diffused resistor in the integrated circuit. Moreover the characteristics of the proposed circuit are independent of the threshold voltage. We have simulated the proposed circuit by using HSPICE. Finally, we have confirmed that the proposed circuit is useful as an analog component.
- 社団法人電子情報通信学会の論文
- 2002-02-01
著者
-
ASAI Hideki
Dept. of Systems Eng., Shizuoka University
-
Asai H
Shizuoka Univ. Hamamatsu‐shi Jpn
-
Asai Hideki
Department Of Systems Engineering Faculty Of Engineering Shizuoka University
-
Asai Hideki
Shizuoka Univ. Hamamatsu‐shi Jpn
-
Asai Hideki
Department Of Opto-electronics&mechanical Engineering Faculty Of Engineering Shizuoka University
-
YONEYAMA Teru
Department of Systems Engineering, Faculty of Engineering, Shizuoka University
-
TANTRY Shashidhar
Department of System Engineering,Faculty of Engineering,Shizuoka University
-
OURA Takao
Department of System Engineering,Faculty of Engineering,Shizuoka University
-
YONEYAMA Teru
System LSI Division,NEC Electronics
-
Yoneyama Teru
System Lsi Division Nec Electronics
-
Oura Takao
Department Of System Engineering Faculty Of Engineering Shizuoka University
-
Tantry Shashidhar
Department Of System Engineering Faculty Of Engineering Shizuoka University
-
Asai Hideki
Department Of Applied Chemistry Faculty Of Engineering Okayama University
関連論文
- An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit
- Fast Simulation Technique of Plane Circuits via Two-Layer CNN-Based Modeling
- An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit
- Matrix Order Reduction by Nodal Analysis Formulation and Relaxation-Based Fast Simulation for Power/Ground Plane
- Fast Simulation Technique of Plane Circuits via Two-Layer CNN-Based Modeling
- CMOS Circuit Simulation Using Latency Insertion Method
- Acceleration of ADI-FDTD Method by Gauss-Seidel Relaxation Approach
- Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog Algorithm(Analog Circuit Techniques and Related Topics)
- An Enhanced Time-Domain Circuit Simulation Technique Based on LIM(Numerical Analysis and Optimization)
- An Efficient Simulation Method of Linear/Nonlinear Mixed Circuits Based on Hybrid Model Order Reduction Technique(Nonlinear Theory and its Applications)
- An Efficient Simulator for Multiport Interconnects with Model Order Reduction Technique(Special Section on Papers Selected from ITC-CSCC 2001)
- A New Methodology for Optimal Placement of Decoupling Capacitors on Printed Circuit Board
- Transient Analysis for Transmission Line Networks Using Expanded GMC (Special Section on Nonlinear Theory and Its Applications)
- Relaxation-Based Transient Analysis of Lossy Coupled Transmission Lines Circuits Using Delay Evaluation Technique(Special Section of Papers Selected from ITC-CSCC'97)
- A Neuro-Based Optimization Algorithm for Three Dimensional Cylindric Puzzles (Special Section of Papers Selected from ITC-CSCC'96)
- 正負両方の抵抗値を持つフローティングレジスタの設計
- フローティングレジスタの設計とその応用
- Design Method of Neural Networks for Limit Cycle Generator by Linear Programming
- A Fast Neural Network Simulator for State Transition Analysis (Special Section on Nonlinear Theory and Its Applications)
- A Fast Algorithm for Spatiotemporal Pattern Analysis of Neural Networks with Multivalued Logic (Special Section on Nonlinear Theory and Its Applications)
- A Neuro-Based Optimization Algorithm for Rectangular Puzzles(Special Section of Papers Selected from ITC-CSCC'97)
- Neural Networks for Digital Sequential Circuits
- Mixed Mode Circuit Simulation Using Dynamic Network Separation and Selective Trace (Special Section on the 6th Karuizawa Workshop on Circuits and Systems)
- Mixed Mode Circuit Simulation Using Dynamic Partitioning (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)
- New Criteria of Selective Orthogonal Matrix Least-Squares Method for Macromodeling Multiport Networks Characterized by Sampled Data(Analog Circuit Techniques and Related Topics)
- A Low Voltage Floating Resistor Circuit Having Both Positive and Negative Resistance Values
- Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally(Special Section on Papers Selected from ITC-CSCC 2001)
- A Structure to realize various kinds of floating resistors
- A CMOS Floating Resistor Circuit Having Both Positive and Negative Resistance Values(Special Section on Analog Circuit Techniques and Relate)
- A Positive Negative Resistor for Synaptic Weights
- A Positive Floating Resistor and A Negative Floating Resistor for the Analog Neural Network Implementation
- A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain(Special Section on Analog Circuit Techniques and Relate)
- An Approach for Practical Use of Common-Mode Noise Reduction Technique for In-Vehicle Electronic Equipment
- Effect of Clinicians' Experience on Chair Time and the Number of Denture Adjustment Visits Required for Complete Denture Treatment
- Macromodel Generation for Hybrid Systems Consisting of Electromagnetic Systems and Lumped RLC Circuits Based on Model Order Reduction(Analog Circuit Techniques and Related Topics)
- Acceleration techniques for Transient Simulation of Lossy Interconnects based on Waveform Relaxation Approach
- A Framework for Macromodeling and Mixed-Mode Simulation of Circuits/Interconnects and Electromagnetic Radiations
- A New Entry to Difluoromethylene Compounds; An Electrochemical Method