Matrix Order Reduction by Nodal Analysis Formulation and Relaxation-Based Fast Simulation for Power/Ground Plane

スポンサーリンク

概要

• 論文の詳細を見る

• This paper describes the matrix order reduction method by the nodal analysis formulation and the application of relaxation-based simulation technique to interconnect and plane networks. First, the characteristics of the power/ground plane networks are considered. Next, the formulation of the plane network by nodal analysis (NA) method is suggested. Furthermore, application and estimation results of the relaxation-based numerical analyses are shown. Finally, it is confirmed that the relaxationbased methods improved by the suggested formulation are much more efficient than the conventional direct-based methods.

• （社）電子情報通信学会の論文
• 2008-09-01

著者

• ASAI Hideki

  Dept. of Systems Eng., Shizuoka University

• TANJI Yuichi

  Dept. of Electrical and Electronic Engineering, Tokushima University

• Asai Hideki

  Dept. Of Systems Eng. Shizuoka University

• SEKINE Tadatoshi

  Dept. of Systems Eng., Shizuoka University

• Tanji Yuichi

  Dept. Of Rise Kagawa University

• Sekine Tadatoshi

  Dept. Of Systems Eng. Shizuoka University

• Tanji Yuichi

  Dept. Of Electrical And Electronic Engineering Sophia University

関連論文

• An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit
• セルラーニューラルネットワークによるプログレッシブ画像復元
• 多値出力関数を有するセルラーニューラルネットワーク
• セルラーニューラルネットワークの受動性
• 離散時間セルラーニューラルネットワーク画像処理プロセッサの設計
• セルラーニューラルネットワークによる非直交ウェーブレット変換
• Sparse GRBFネットワークを用いた画像符号化法
• Analysis of Two Dimensional Circuits Based on Multi-Conductor Theorem
• RBFネットワークを用いた画像符号化手法の拡張
• RBFネットワークを用いた画像符号化手法の一般化
• 回路解析技法を用いた冗長自由度を有する運動ダイナミクスの制御
• 適応型最小2乗法の拡張について
• CNNによる準可逆化伝送方式 : 「美」の圧縮再生について
• A-2-3 階層型DT-CNNの高速化について
• Controlling Initial State of Cooperative and Competitive Cellular Neural Networks
• An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit
• Matrix Order Reduction by Nodal Analysis Formulation and Relaxation-Based Fast Simulation for Power/Ground Plane
• CMOS Circuit Simulation Using Latency Insertion Method
• Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog Algorithm(Analog Circuit Techniques and Related Topics)
• An Enhanced Time-Domain Circuit Simulation Technique Based on LIM(Numerical Analysis and Optimization)
• An Efficient Simulation Method of Linear/Nonlinear Mixed Circuits Based on Hybrid Model Order Reduction Technique(Nonlinear Theory and its Applications)
• An Efficient Simulator for Multiport Interconnects with Model Order Reduction Technique(Special Section on Papers Selected from ITC-CSCC 2001)
• A New Methodology for Optimal Placement of Decoupling Capacitors on Printed Circuit Board
• Transient Analysis for Transmission Line Networks Using Expanded GMC (Special Section on Nonlinear Theory and Its Applications)
• Relaxation-Based Transient Analysis of Lossy Coupled Transmission Lines Circuits Using Delay Evaluation Technique(Special Section of Papers Selected from ITC-CSCC'97)
• 協調競合ネットワークを用いたDT-CNNブロックマッチング
• Design Method of Neural Networks for Limit Cycle Generator by Linear Programming
• A Fast Neural Network Simulator for State Transition Analysis (Special Section on Nonlinear Theory and Its Applications)
• A Fast Algorithm for Spatiotemporal Pattern Analysis of Neural Networks with Multivalued Logic (Special Section on Nonlinear Theory and Its Applications)
• A Neuro-Based Optimization Algorithm for Rectangular Puzzles(Special Section of Papers Selected from ITC-CSCC'97)
• New Criteria of Selective Orthogonal Matrix Least-Squares Method for Macromodeling Multiport Networks Characterized by Sampled Data(Analog Circuit Techniques and Related Topics)
• A Low Voltage Floating Resistor Circuit Having Both Positive and Negative Resistance Values
• Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally(Special Section on Papers Selected from ITC-CSCC 2001)
• A Structure to realize various kinds of floating resistors
• A CMOS Floating Resistor Circuit Having Both Positive and Negative Resistance Values(Special Section on Analog Circuit Techniques and Relate)
• A Positive Negative Resistor for Synaptic Weights
• A Positive Floating Resistor and A Negative Floating Resistor for the Analog Neural Network Implementation
• Reduced-Order Modeling of Interconnect Networks via Dominant Poles Extraction Using Orthogonal Least Square Method
• 離散時間セルラニューラルネットワークを用いた静止画像の中間調表現 (「非線形信号処理」特集号)
• An Approach for Practical Use of Common-Mode Noise Reduction Technique for In-Vehicle Electronic Equipment
• Controlling Initial State of Cooperative and Competitive Cellular Neural Networks
• CNN with Multi-Level Hysteresis Quantization Output

もっと見る 閉じる

スポンサーリンク