Neural Networks for Digital Sequential Circuits
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概要
- 論文の詳細を見る
In this letter an SR-latch circuit using Hopfield neural networks is introduced. An energy function suited for a neural SR-latch circuit is defined for which the global convergence is guaranteed. We also demonstrate how to compose master-slave (M/S) SR- and JK-flip flops of novel SR-latch circuits, and further an asynchronous binary counter of M/S JK-flip flops. Computer simulations are included to illustrate how each presented circuit operates.
- 社団法人電子情報通信学会の論文
- 1994-12-25
著者
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Asai Hideki
Department Of Systems Engineering Faculty Of Engineering Shizuoka University
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Asai Hideki
Faculty Of Engineering Shizuoka University
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NINOMIYA Hiroshi
Faculty of Engineering, Shizuoka University
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Ninomiya Hiroshi
Faculty Of Engineering Shizuoka University
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