Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits
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概要
- 論文の詳細を見る
A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.
- IEICE - The Institute of Electronics, Information and Communication Engineersの論文
- 2009-02-01
著者
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AMEMIYA Yoshihito
Department of Electrical Engineering, Hokkaido University
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Amemiya Yoshihito
Graduate School Of Information Sci. & Technol. Hokkaido Univ.
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Hirose Tetsuya
Department of Electrical and Electronics Engineering, Kobe University
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Asai Tetsuya
Department of Electrical Engineering, Hokkaido University
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Asai Tetsuya
Graduate School Of Information Science And Technology Hokkaido University
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Hirose Tetsuya
Department Of Electrical And Electronics Engineering Kobe University
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OGAWA Taichi
Department of Electrical Engineering, Hokkaido University
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Amemiya Yoshihito
Department Of Electrical Engineering Faculty Of Engineering Hokkaido University
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Asai Tetsuya
Department Of Electrical And Electronic Engineering Toyohashi University Of Technology
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Hirose Tetsuya
Department Of Electrical Engineering Hokkaido University
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Ogawa Taichi
Department Of Electrical Engineering Hokkaido University
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Amemiya Yoshihito
Graduate School Of Information Science And Technology Hokkaido University
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Hirose Tetsuya
Department of Electrical and Electronic Engineering, Graduate School of Engineering, Kobe University, 1-1 Rokkodai, Nada, Kobe 657-8501, Japan
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