An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits(Neuron and Neural Networks,<Special Section>Nonlinear Theory and its Applications)
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概要
- 論文の詳細を見る
We designed subthreshold analog MOS circuits implementing an inhibitory network model that performs noise-shaping pulsedensity modulation (PDM) with noisy neural elements, with the aim of developing a possible ultralow-power one-bit analog-to-digital converter. The static and dynamic noises given to the proposed circuits were obtained from device mismatches of current sources (transistors) and externally applied random spike currents, respectively. Through circuit simulations we confirmed that the circuit exhibited noise-shaping properties, and signal-to-noise ratio (SNR) of the network was improved by 7.9dB compared with that of the uncoupled network as a result of noise shaping.
- 社団法人電子情報通信学会の論文
- 2007-10-01
著者
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Amemiya Yoshihito
Graduate School Of Information Sci. & Technol. Hokkaido Univ.
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Asai Tetsuya
Graduate School Of Information Science And Technology Hokkaido University
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HIROSE Tetsuya
Graduate School of Engineering, Osaka University
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Hirose Tetsuya
Department Of Electrical And Electronics Engineering Kobe University
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Hirose Tetsuya
Graduate School Of Engineering Kobe University
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UTAGAWA Akira
Graduate School of Information Science and Technology, Hokkaido University
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Hirose Tetsuya
Department Of Electrical Engineering Hokkaido University
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Utagawa Akira
Graduate School Of Information Science And Technology Hokkaido University
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Amemiya Yoshihito
Graduate School Of Information Science And Technology Hokkaido University
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