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Semiconductor Leading Edge Technologies Inc. (selete) | 論文
- Fabrication of 65-nm Holes for 157-nm Lithography
- Application of Electron Projection Lithography to Via Formation in Two-Layer Metallization
- Performance and Reliability Improvement by Optimized Nitrogen Content of TaSiNx Metal Gate in Metal/HfSiON nFETs
- Novel via Chain Structure for Failure Analysis at 65 nm-Node Fixing OPC Using Inner and Outer via Chain Dummy Patterns(Microelectronic Test Structures)
- Characterization of Low-k Interconnect Dielectrics by EELS
- Nano-meter order Structures of Porous Low-k Films and their Impacts on Cu/Low-k Processes
- Characterization of Fluoropolymer Resist for 157-nm Lithography
- Application of a New BARC Material for 157-nm Lithography
- A study of an Organic Bottom Antireflective Coating for 157-nm Lithography
- Material Selection for the Metal Gate/High-k Transistors
- SiOCH Films with Hydrocarbon Network Bonds : First-Principles Investigation
- Hydrocarbon Groups and Film Properties of SiOCH Dielectrics : Theoretical Investigations using Molecular Models
- Relationship between Chemical Gradient and Line Edge Roughness of Chemically Amplified Extreme Ultraviolet Resist
- Fabrication of 70-nm-Pitch Two-Level Interconnects by using Extreme Ultraviolet Lithography
- Assessment and extendibility of chemically amplified resists for extreme ultraviolet lithography: consideration of nanolithography beyond 22nm half-pitch
- Fabrication of 65-nm Holes for 157-nm Lithography
- Area Selective Flash Lamp Post-Deposition Annealing of High-k Film Using Si Photo Absorber for Metal Gate MISFETs with NiSi Source/Drain
- High-Etching-Selectivity Barrier SiC ($k
- Galvanic Corrosion Control in Chemical Mechanical Polishing of Cu Interconnects with Ruthenium Barrier Metal Film
- Study of a Negative Threshold Voltage Shift in Positive Bias Temperature Instability and a Positive Threshold Voltage Shift the Negative Bias Temperature Instability of Yttrium-Doped HfO2 Gate Dielectrics