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Semiconductor Leading Edge Technologies Inc. (selete) | 論文
- Impact of Activation Annealing Temperature on the Performance, Negative Bias Temperature Instability, and Time-to-Dielectric Breakdown Lifetime of High-$k$/Metal Gate Stack p-Type Metal–Oxide–Semiconductor Field Effect Transistors
- Multicomponent negative-type photoresist based on Noria analog with 12 ethoxy groups
- Improvement of Device Characteristics for TiN Gate p-Type Metal–Insulator–Semiconductor Field-Effect Transistor with Al2O3-Capped HfO2 Dielectrics by Controlling Al2O3 Diffusion Annealing Process
- Journal of Photopolymer Science and Technology Award
- 193nm Lithography with Novel Highly Transparent Acid Amplifier for Chemically Amplified Resists
- Vestiges of Multiple Progressive Dielectric Breakdown on HfSiON Surfaces
- Dual-Metal Gate Technology with Metal-Inserted Full Silicide Stack and Ni-Rich Full Silicide Gate Electrodes Using a Single Ni-Rich Full Silicide Phase for Scaled High-$k$ Complementary Metal–Oxide–Semiconductor Field-Effect Transistors
- Suppression of Metamorphoses of Metal/High-$k$ Gate Stack by Low-Temperature, Cl-Free SiN Offset Spacer, and Its Impact on Scaled Metal–Oxide–Semiconductor Field-Effect Transistors
- Hole Mobility Enhancement Caused by Gate-Induced Vertical Strain in Gate-First Full-Metal High-$k$ P-Channel Field Effect Transistors Using Ion-Beam W
- Analysis of Dose-Pitch Matrices of Line Width and Edge Roughness of Chemically Amplified Fullerene Resist
- Etch-Byproduct Pore Sealing for Atomic-Layer-Deposited-TaN Deposition on Porous Low-$k$ Film
- Effect of Dissolved Oxygen on Cu Corrosion in Single Wafer Cleaning Process
- Cathode Electron Injection Breakdown Model and Time Dependent Dielectric Breakdown Lifetime Prediction in High-$k$/Metal Gate Stack p-Type Metal–Oxide–Silicon Field Effect Transistors
- Impact of High Temperature Annealing on Traps in Physical-Vapor-Deposited-TiN/SiO2/Si Analyzed by Positron Annihilation
- Origin of the Hole Current in n-type High-$k$/Metal Gate Stacks Field Effect Transistor in an Inversion State
- Trap-Related Carrier Transports in p-Channel Field-Effect Transistor with Polycrystalline Si/HSiON Gate Stack
- Comprehensive Analysis of Positive and Negative Bias Temperature Instabilities in High-$k$/Metal Gate Stack Metal–Oxide–Silicon Field Effect Transistors with Equivalent Oxide Thickness Scaling to Sub-1 nm
- Modified Oxygen Vacancy Induced Fermi Level Pinning Model Extendable to P-Metal Pinning
- Ultraviolet-Curing Mechanism of Porous-SiOC
- Performance and Reliability Improvement by Optimizing the Nitrogen Content of the TaSiNx Metal Gate in Metal/HfSiON n-Type Field-Effect Transistors