Effect of gate-recess structure on electron transport in InP-based high electron mobility transistors studied by Monte Carlo simulations

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概要

• 論文の詳細を見る
• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文

著者

• Endoh A

  Fujitsu Lab. Ltd. Atsugi Jpn

• Matsui Toshiaki

  Communications Research Laboratory Ministry Of Posts And Telecommunications

• Watanabe Issei

  National Institute Of Information And Communications Technology (nict)

• Mimura Takashi

  National Institute Of Information And Communications Technology (nict)

• Mimura T

  National Institute Of Information And Communications Technology

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• Effect of gate-recess structure on electron transport in InP-based high electron mobility transistors studied by Monte Carlo simulations

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