Method for Detecting Defects in Silicon-On-Insulator Using Capacitance Transient Spectroscopy
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概要
- 論文の詳細を見る
A method for detecting defects such as interface states and a deep trap in Si-on-insulator (SOI) has been proposed, which is based on deep-level transient spectroscopy (DLTS) analysis of the metal-oxide semiconductor (MOS) structure. It is shown, for a bonded p-type SOI wafer consisting of 5 μm top-Si (T-Si) and 1 μm buried oxide (BOX) layers, that the interface state densities between T-Si/BOX and BOX/back-Si (B-Si) can be measured. Furthermore, the validity of this DLTS technique for the detection of a discrete deep level has been confirmed by using a Fe-doped SOI wafer. It is shown that the Fe concentration in B-Si is consistent with that of bulk Si, while the Fe concentration in T-Si shows significant enhancement. Through these investigations of SOI wafers, the validity of this DLTS method has been demonstrated.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2004-05-15
著者
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WANG Dong
Art, Science and Technology Center for Cooperative Research, Kyushu University
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NAKASHIMA Hiroshi
Art, Science and Technology Center for Cooperative Research, Kyushu University
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ZHAO Liwei
Art, Science and Technology Center for Cooperative Research, Kyushu University
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NOGUCHI Takashi
Interdisciplinary Graduate School of Engineering Sciences, Kyushu University
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ITANI Kousuke
Interdisciplinary Graduate School of Engineering Sciences, Kyushu University
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WANG Junli
Art, Science and Technology Center for Cooperative Research, Kyushu University
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Wang Junli
Art, Science and Technology Center for Cooperative Research, Kyushu University, Kasuga, Fukuoka 816-8580, Japan
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Itani Kousuke
Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, Kasuga, Fukuoka 816-8580, Japan
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Nakashima Hiroshi
Art, Science and Technology Center for Cooperative Research, Kyushu University, Kasuga, Fukuoka 816-8580, Japan
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