A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST
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概要
- 論文の詳細を見る
This paper presents a new low power BIST TPG scheme for reducing scan transitions. It uses a transition freezing and melting method which is implemented of the transition freezing block and a MUX. When random test patterns are generated from an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique freezes transitions of patterns using a freezing value. Experimental results show that the proposed BIST TPG schemes can reduce average power reduction by about 60% without performance loss and peak power by about 30% in ISCAS89 benchmark circuits.
- （社）電子情報通信学会の論文
- 2008-04-01
著者
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Kang Sungho
Department of Electrical & Electronic Engineering, Yonsei University
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Kang Sungho
Dept. Of Electrical And Electronic Eng. Yonsei Univsersity
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KIM Youbean
Yonsei University
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KIM Youbean
Department of Electrical and Electronic Engineering, Yonsei University
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KIM Kicheol
Department of Electrical and Electronic Engineering, Yonsei University
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KIM Incheol
Department of Electrical and Electronic Engineering, Yonsei University
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SON Hyunwook
Department of Electrical and Electronic Engineering, Yonsei University
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Son Hyeonuk
Yonsei University
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Kim Incheol
Department Of Electrical And Electronic Engineering Yonsei University
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Kim Kicheol
Department Of Electrical And Electronic Engineering Yonsei University
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