A New Low Power Test Pattern Generator for BIST Architecture(Semiconductor Materials and Devices)
スポンサーリンク
概要
- 論文の詳細を見る
A new low power test pattern generator (TPG) which can effectively reduce the average power consumption during test application is developed. The new TPG reduces the weighted switching activity (WSA) of the circuit under test (CUT) by suppressing transitions at some primary inputs which make many transitions. Moreover, the new TPG does not lose fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 33.8% while achieving high fault coverage.
- 社団法人電子情報通信学会の論文
- 2005-10-01
著者
-
Kang Sungho
Department of Electrical & Electronic Engineering, Yonsei University
-
Kang Sungho
Dept. Of Electrical And Electronic Eng. Yonsei Univsersity
-
KIM Kicheol
Department of Electrical and Electronic Engineering, Yonsei University
-
KIM Incheol
Department of Electrical and Electronic Engineering, Yonsei University
-
SONG Dongsub
Department of Electrical and Electronic Engineering, Yonsei Univsersity
-
Song Dongsub
Department Of Electrical And Electronic Engineering Yonsei Univsersity
-
Kim Incheol
Department Of Electrical And Electronic Engineering Yonsei University
-
Kim Kicheol
Department Of Electrical And Electronic Engineering Yonsei University
関連論文
- A high performance network-on-chip scheme using lossless data compression
- A Fast IP Address Lookup Algorithm Based on Search Space Reduction
- A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection
- MTR-Fill : A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs
- A Pattern Partitioning Algorithm for Memory-Efficient Parallel String Matching in Deep Packet Inspection
- An Effective Programmable Memory BIST for Embedded Memory
- Selective Scan Slice Grouping Technique for Efficient Test Data Compression
- A Selective Scan Chain Activation Technique for Minimizing Average and Peak Power Consumption
- Grouped Scan Slice Repetition Method for Reducing Test Data Volume and Test Application Time
- A New Built-in Self Test Scheme for Phase-Locked Loops Using Internal Digital Signals
- An Effective Built-In Self-Test for Chargepump PLL(Papers Selected from AP-ASIC 2004)
- Pattern Mapping Method for Low Power BIST Based on Transition Freezing Method
- A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters
- A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST
- A New Analog-to-Digital Converter BIST Considering a Transient Zone(Integrated Electroics)
- A New Low Power Test Pattern Generator for BIST Architecture(Semiconductor Materials and Devices)
- A Low-Power Implementation Scheme of Interpolation FIR Filters Using Distributed Arithmetic(Integrated Electronics)
- An Acceleration Processor for Data Intensive Scientific Computing(Scientific and Engineering Computing with Applications)(Hardware/Software Support for High Performance Scientific and Engineering Computing)
- Efficient Test Generation Using Redundancy Identification
- A Clustered RIN BIST Based on Signal Probabilities of Deterministic Test Sets(Dependable Computing)