A Clustered RIN BIST Based on Signal Probabilities of Deterministic Test Sets(Dependable Computing)
スポンサーリンク
概要
- 論文の詳細を見る
In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST that can improve the embedding probabilities of random-pattern-resistant-patterns. A simulated annealing based algorithm that maximizes the embedding probabilities of scan test cubes has been developed to reorder scan cells. Experimental results demonstrate that the proposed CRIN BIST technique reduces test time by 35% and the storage requirement by 39% in comparison with previous work.
- 社団法人電子情報通信学会の論文
- 2006-01-01
著者
-
Kang Sungho
Department of Electrical & Electronic Engineering, Yonsei University
-
Kang Sungho
Dept. Of Electrical & Electronic Eng. Yonsei University
-
Song Dong-sup
Department Of Electrical And Electronic Engineering Yonsei University
-
Song Dong‐sup
Yonsei Univ. Kor
関連論文
- A high performance network-on-chip scheme using lossless data compression
- A Fast IP Address Lookup Algorithm Based on Search Space Reduction
- A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection
- MTR-Fill : A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs
- A Pattern Partitioning Algorithm for Memory-Efficient Parallel String Matching in Deep Packet Inspection
- An Effective Programmable Memory BIST for Embedded Memory
- Selective Scan Slice Grouping Technique for Efficient Test Data Compression
- A Selective Scan Chain Activation Technique for Minimizing Average and Peak Power Consumption
- Grouped Scan Slice Repetition Method for Reducing Test Data Volume and Test Application Time
- A New Built-in Self Test Scheme for Phase-Locked Loops Using Internal Digital Signals
- An Effective Built-In Self-Test for Chargepump PLL(Papers Selected from AP-ASIC 2004)
- A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters
- A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST
- A New Analog-to-Digital Converter BIST Considering a Transient Zone(Integrated Electroics)
- A New Low Power Test Pattern Generator for BIST Architecture(Semiconductor Materials and Devices)
- A Low-Power Implementation Scheme of Interpolation FIR Filters Using Distributed Arithmetic(Integrated Electronics)
- An Acceleration Processor for Data Intensive Scientific Computing(Scientific and Engineering Computing with Applications)(Hardware/Software Support for High Performance Scientific and Engineering Computing)
- Efficient Test Generation Using Redundancy Identification
- A Clustered RIN BIST Based on Signal Probabilities of Deterministic Test Sets(Dependable Computing)
- An Efficient IP Address Lookup Scheme Using Balanced Binary Search with Minimal Entry and Optimal Prefix Vector
- An accurate diagnosis of transition fault clusters based on single fault simulation
- A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection