A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection

スポンサーリンク

概要

• 論文の詳細を見る

• This paper presents for hardware-based parallel pattern matching scheme that adopts heterogeneous bit-split string matchers for deep packet inspection (DPI) devices. Considering the pattern lengths, a set of target patterns is partitioned into two subsets for short and long patterns. By adopting the appropriate bit-split string matcher types for the two subsets, the memory requirements can be optimized for the bit-split parallel pattern matching engine. Experimental results show that the total memory requirements decrease by 39.40% and 20.52%, in comparison with the existing bit-split pattern matching approaches.

• The Institute of Electronics, Information and Communication Engineersの論文

著者

• Kang Sungho

  Dept. Of Electrical & Electronic Eng. Yonsei University

• AHN Jin-Ho

  Dept. of Electronic Eng., Hoseo University

• BAEK Dongmyoung

  Broadcasting and Telecommunication Convergence Research Laboratory

• Ahn Jin-ho

  Dept. Of Electronic Eng. Hoseo University

• Kim Hyunjin

  Dept. Of Electrical And Electronic Eng. Yonsei University

• Hong Hyejeong

  Dept. Of Electrical And Electronic Eng. Yonsei Univ.

• Baek Dongmyoung

  Broadcasting and Telecommunication Convergence Research Lab.

関連論文

• A Fast IP Address Lookup Algorithm Based on Search Space Reduction
• A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection
• MTR-Fill : A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs
• A Pattern Partitioning Algorithm for Memory-Efficient Parallel String Matching in Deep Packet Inspection
• Selective Scan Slice Grouping Technique for Efficient Test Data Compression
• A Selective Scan Chain Activation Technique for Minimizing Average and Peak Power Consumption
• Grouped Scan Slice Repetition Method for Reducing Test Data Volume and Test Application Time
• A New Built-in Self Test Scheme for Phase-Locked Loops Using Internal Digital Signals
• A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters
• A New Analog-to-Digital Converter BIST Considering a Transient Zone(Integrated Electroics)
• Efficient Test Generation Using Redundancy Identification
• A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection
• A Clustered RIN BIST Based on Signal Probabilities of Deterministic Test Sets(Dependable Computing)
• An Efficient IP Address Lookup Scheme Using Balanced Binary Search with Minimal Entry and Optimal Prefix Vector
• An accurate diagnosis of transition fault clusters based on single fault simulation
• A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection

もっと見る 閉じる

スポンサーリンク