A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection

スポンサーリンク

概要

• 論文の詳細を見る

• This paper proposes a new pattern matching architecture with multi-character processing for deep packet inspection. The proposed pattern matching architecture detects the start point of pattern matching from multi-character input using input text alignment. By eliminating duplicate hardware components using process element tree, hardware cost is greatly reduced in the proposed pattern matching architecture.

• （社）電子情報通信学会の論文
• 2010-09-01

著者

• Kang Sungho

  Dept. Of Electrical And Electronic Eng. Yonsei University

• KIM Hyunjin

  Dept. of Electrical and Electronic Eng., Yonsei University

• AHN Jin-Ho

  Dept. of Electronic Eng., Hoseo University

• HONG Hyejeong

  Dept. of Electrical and Electronic Eng., Yonsei University

• BAEK Dongmyoung

  Broadcasting and Telecommunication Convergence Research Laboratory

• Ahn Jin-ho

  Dept. Of Electronic Eng. Hoseo University

• Kim Hyunjin

  Yonsei Univ. Kor

• Kim Hyunjin

  Dept. Of Electrical And Electronic Eng. Yonsei University

• Hong Hyejeong

  Dept. Of Electrical And Electronic Eng. Yonsei University

• AHN Seongyong

  School of Electrical & Electronic Eng., Yonsei University

• HONG Hyejeong

  School of Electrical & Electronic Eng., Yonsei University

• KIM HyunJin

  School of Electrical & Electronic Eng., Yonsei University

• AHN Jin-Ho

  Dep. of Electronic Eng., Hoseo University

• BAEK Dongmyong

  Next Generation Ethernet Research Team, ETRI

• KANG Sungho

  School of Electrical & Electronic Eng., Yonsei University

• Ahn Seongyong

  School Of Electrical & Electronic Eng. Yonsei University

• Kang Sungho

  Dept. Of Electrical And Electronic Eng. Yonsei Univ.

• Hong Hyejeong

  Dept. Of Electrical And Electronic Eng. Yonsei Univ.

関連論文

• A Fast IP Address Lookup Algorithm Based on Search Space Reduction
• A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection
• MTR-Fill : A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs
• A Pattern Partitioning Algorithm for Memory-Efficient Parallel String Matching in Deep Packet Inspection
• A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection
• An Efficient IP Address Lookup Scheme Using Balanced Binary Search with Minimal Entry and Optimal Prefix Vector
• Thermal-aware dynamic voltage frequency scaling for many-core processors under process variations
• Acceleration of Deep Packet Inspection Using a Multi-Byte Processing Prefilter
• Dynamic thermal management for 3D multicore processors under process variations
• A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection

スポンサーリンク