A Fast IP Address Lookup Algorithm Based on Search Space Reduction
スポンサーリンク
概要
- 論文の詳細を見る
This letter proposes a fast IP address lookup algorithm based on search space reduction. Prefixes are classified into three types according to the nesting relationship and a large forwarding table is partitioned into multiple small trees. As a result, the search space is reduced. The results of analyses and experiments show that the proposed method offers higher lookup and updating speeds along with reduced memory requirements.
- （社）電子情報通信学会の論文
- 2010-04-01
著者
-
Kang Sungho
Dept. Of Electrical And Electronic Eng. Yonsei Univsersity
-
Kang Sungho
Dept. Of Electrical And Electronic Eng. Yonsei University
-
Kang Sungho
Dept. Of Electrical & Electronic Eng. Yonsei University
-
PARK Hyuntae
Dept. of Electrical and Electronic Eng., Yonsei University
-
KIM Hyunjin
Dept. of Electrical and Electronic Eng., Yonsei University
-
KIM Hong-Sik
Dept. of Electrical and Electronic Eng., Yonsei University
-
Kim Hyunjin
Yonsei Univ. Kor
-
Kim Hyunjin
Dept. Of Electrical And Electronic Eng. Yonsei University
-
Park Hyuntae
Dept. Of Electrical And Electronic Eng. Yonsei University
-
Kang Sungho
Dept. Of Electrical And Electronic Eng. Yonsei Univ.
-
Park Hyuntae
Dept. Of Electrical And Electronic Eng. Yonsei Univ.
関連論文
- A Fast IP Address Lookup Algorithm Based on Search Space Reduction
- A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection
- MTR-Fill : A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs
- A Pattern Partitioning Algorithm for Memory-Efficient Parallel String Matching in Deep Packet Inspection
- Selective Scan Slice Grouping Technique for Efficient Test Data Compression
- A Selective Scan Chain Activation Technique for Minimizing Average and Peak Power Consumption
- Grouped Scan Slice Repetition Method for Reducing Test Data Volume and Test Application Time
- A New Built-in Self Test Scheme for Phase-Locked Loops Using Internal Digital Signals
- Pattern Mapping Method for Low Power BIST Based on Transition Freezing Method
- A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters
- A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST
- A New Analog-to-Digital Converter BIST Considering a Transient Zone(Integrated Electroics)
- A New Low Power Test Pattern Generator for BIST Architecture(Semiconductor Materials and Devices)
- Efficient Test Generation Using Redundancy Identification
- A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection
- A Clustered RIN BIST Based on Signal Probabilities of Deterministic Test Sets(Dependable Computing)
- An Efficient IP Address Lookup Scheme Using Balanced Binary Search with Minimal Entry and Optimal Prefix Vector
- An accurate diagnosis of transition fault clusters based on single fault simulation
- A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection