A high performance network-on-chip scheme using lossless data compression
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概要
- 論文の詳細を見る
A new NoC (network on chip) architecture using lossless data compression and decompression to improve the performance and power efficiency of the on-chip interconnect is proposed. In the proposed NoC scheme, the sender compresses the data to be transferred in order to reduce the number of data packets and the receiver decompresses the encoded data to restore the original data. For the lossless compression and decompression, we have implemented a hardware CODEC based on a Golomb-Rice algorithm. According to the experimental results using a cycle-accurate NoC simulator, the proposed scheme could significantly improve the performance and power efficiency of the conventional NoC architecture.
著者
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Kim Hong-Sik
Department of Electrical & Electronic Engineering, Yonsei University
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Jung Youngha
Samgsung Electronics Co. Ltd.
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Kim Hyunjin
Department of Electrical & Electronic Engineering, Yonsei University
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Ahn Jin-Ho
Department of Electronic Engineering, Hoseo University
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Park Woo-Chan
Department of Computer Science, Sejong University
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Kang Sungho
Department of Electrical & Electronic Engineering, Yonsei University
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Park Woo-chan
Department Of Computer Science Yonsei University
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Ahn Jin-ho
Department Of Electronic Engineering Hoseo University
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Kim Hyunjin
Department of Chemical Engineering, Kyung Hee University, Yongin, Gyeonggi-do 446-701, Republic of Korea
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Kim Hyunjin
Department of Electrical & Electronic Engineering, Yonsei University
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Park Woo-Chan
Department of Computer Engineering, Sejong University
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