Design of the Floating-Point Adder Supporting the Format Conversion and the Rounding Operations with Simultaneous Rounding Scheme(Regular Section)

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概要

• 論文の詳細を見る

• The format conversion operations between a floating-point number and an integer number and a round operation are the important standard floating-point operations. In most cases, these operations are implemented by adding additional hardware to the floating-point adder. The SR (simultaneous rounding) method, one of the techniques used to improve the performance of the floating-point adder, can perform addition and rounding operations at the same stage and is an efficient method with respect to the silicon area and its performance. In this paper, a hardware model to execute CRops (conversion and rounding operations) for the SR floating-point adder is presented and CRops are analyzed on the proposed hardware model. Implementation details are also discussed. The proposed scheme can maintain the advantages of the SR method and can perform each CRop with three pipeline stages.

• 社団法人電子情報通信学会の論文
• 2002-07-25

著者

• Park Woo-chan

  Department Of Computer Science Yonsei University

• Han Tack-Don

  Department of Computer Science, Yonsei University

• Han Tack-don

  Department Of Computer Science Yonsei University

• JEONG Cheol-Ho

  Department of Computer Science, Yonsei University

• Jeong Cheol-ho

  Department Of Computer Science Yonsei University

• Park Woo-Chan

  Department of Computer Engineering, Sejong University

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