Cooperative Cache System : A Low Power Cache System for Embedded Processors(Digital,<Special Section>Low-Power, High-Speed LSIs and Related Technologies)

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概要

• 論文の詳細を見る

• This paper presents a dual data cache system structure, called a cooperative cache system, that is designed as a low power cache structure for embedded processors. The cooperative cache system consists of two caches, i.e., a direct-mapped temporal oriented cache (TOC) and a four-way set-associative spatial oriented cache (SOC). The cooperative cache system achieves improvement in performance and reduction in power consumption by virtue of the structural characteristics of the two caches designed inherently to help each other. An evaluation chip of an embedded processor having the cooperative cache system is manufactured by Samsung Electronics Co. with 0.25μm 4-metal process technology.

• 社団法人電子情報通信学会の論文
• 2007-04-01

著者

• Han Tack-Don

  Department of Computer Science, Yonsei University

• PARK Gi-Ho

  Dept. of Computer Engineering, Sejong University

• KIM Shin-Dug

  Dept. of Computer Science, Yonsei University

• Kim Shin-dug

  Dept. Of Computer Science Yonsei University

• Park Gi-ho

  Dept. Of Computer Engineering Sejong University

• Han Tack-don

  Department Of Computer Science Yonsei University

• Kim Shin-dug

  Department Of Computer Scinece Yonsei University

• PARK Gi-Ho

  Processor Architecture Lab., Samsung Electronics

• LEE Kil-Whan

  AP Team, Samsung Electronics

• Lee Kil-whan

  Ap Team Samsung Electronics

• Kim Shin-dug

  Department Of Computer Science Yonsei University

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