A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache
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概要
- 論文の詳細を見る
- 2009-04-01
著者
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Park Jung‐wook
Yonsei Univ. Seoul Kor
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PARK Sung-Bae
Samsung Electronics
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Park Sung-bae
Processor Architecture Lab. Samsung Electronics
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PARK Gi-Ho
Dept. of Computer Engineering, Sejong University
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PARK Jung-Wook
Dept. of Computer Science, Yonsei University
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LEE Hoi-Jin
Processor Architecture Lab. Samsung Electronics
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JUNG Gunok
Processor Architecture Lab. Samsung Electronics
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KIM Shin-Dug
Dept. of Computer Science, Yonsei University
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Kim Shin-dug
Dept. Of Computer Science Yonsei University
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Park Gi-ho
Dept. Of Computer Engineering Sejong University
関連論文
- CMOS Level Converter with Balanced Rise and Fall Delays(Electronic Circuits)
- A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache
- Power and Skew Aware Point Diffusion Clock Network
- Hybrid System Based Interpolation Line Search Optimization Applied to Nonlinear Controller in a Power Network(Hybrid Dynamical Systems,Concurrent/Hybrid Systems: Theory and Applications)
- Low-Power Embedded Processor Design Using Branch Direction
- Floating Point Adder/Subtractor Performing IEEE Rounding and Addition/Subtraction in Parallel
- Cooperative Cache System : A Low Power Cache System for Embedded Processors(Digital,Low-Power, High-Speed LSIs and Related Technologies)