Power and Skew Aware Point Diffusion Clock Network

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概要

• 論文の詳細を見る

• This letter presents point diffusion clock network (PDCN) with local clock tree synthesis (CTS) scheme. The clock network is implemented with ten times wider metal line space than typical mesh networks for low power and utilized to nine times smaller area CTS execution for minimized clock skew amount. The measurement results show that skew amount of PDCN with local CTS is reduced to 36% and latency is shrunk to 45% of the amount in a 4.81mm2 CortexA-8 core with 65nm Samsung process.

• （社）電子情報通信学会の論文
• 2008-11-01

著者

• Park Sung

  Samsung Advanced Institute Of Technology

• Park Sung

  Samsung Electronics

• JUNG Gunok

  Processor Architecture Lab. Samsung Electronics

• JUNG Gunok

  Samsung Electronics

• KIM Chunghee

  Samsung Electronics

• CHAE Kyoungkuk

  Samsung Electronics

• PARK Giho

  Sejong University

関連論文

• A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache
• Power and Skew Aware Point Diffusion Clock Network
• Free Carrier Concentration Gradient along the c-Axis of a Freestanding Si-doped GaN Single Crystal
• Low-Power Embedded Processor Design Using Branch Direction
• Free-Standing GaN Substrates by Hydride Vapor Phase Epitaxy
• Free Carrier Concentration Gradient along the $c$-Axis of a Freestanding Si-doped GaN Single Crystal

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