Low-Power Embedded Processor Design Using Branch Direction

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概要

• 論文の詳細を見る

• This paper presents a wordline gating logic for reducing unnecessary BTB accesses. Partial bit of the branch predictor was simultaneously recorded in the middle of BTB to prevent further SRAM operation. Experimental results with embedded applications showed that the proposed mechanism reduces around 38% of BTB power consumption.

• （社）電子情報通信学会の論文
• 2009-12-01

著者

• Park Jung‐wook

  Yonsei Univ. Seoul Kor

• PARK Gi-Ho

  Dept. of Computer Engineering, Sejong University

• PARK Jung-Wook

  Dept. of Computer Science, Yonsei University

• JUNG Gunok

  Processor Architecture Lab. Samsung Electronics

• KIM Shin-Dug

  Dept. of Computer Science, Yonsei University

• JUNG Gunok

  Samsung Electronics

• Kim Shin-dug

  Dept. Of Computer Science Yonsei University

• Park Gi-ho

  Dept. Of Computer Engineering Sejong University

関連論文

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• Power and Skew Aware Point Diffusion Clock Network
• Hybrid System Based Interpolation Line Search Optimization Applied to Nonlinear Controller in a Power Network(Hybrid Dynamical Systems,Concurrent/Hybrid Systems: Theory and Applications)
• Low-Power Embedded Processor Design Using Branch Direction
• Floating Point Adder/Subtractor Performing IEEE Rounding and Addition/Subtraction in Parallel
• Cooperative Cache System : A Low Power Cache System for Embedded Processors(Digital,Low-Power, High-Speed LSIs and Related Technologies)

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