CMOS Level Converter with Balanced Rise and Fall Delays(Electronic Circuits)
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概要
- 論文の詳細を見る
A novel CMOS level converter with balanced rise and fall delays for arbitrary voltage conversion is presented. The proposed level converter was designed using a 90nm CMOS process technology. The comparison result indicates that the maximum difference between the rise and fall delays of the proposed level converter was reduced by up to 92% compared to the conventional CMOS level converters.
- 社団法人電子情報通信学会の論文
- 2007-01-01
著者
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Kim Min-su
School Of Information And Communication Engineering Sungkyunkwan University:samsung Electronics
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JUN Young-Hyun
Samsung Electronics
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KONG Bai-Sun
School of Information and Communication Engineering, Sungkyunkwan University
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PARK Sung-Bae
Samsung Electronics
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Kong Bai‐sun
School Of Information And Communication Engineering Sungkyunkwan University
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Kong Bai-sun
School Of Information And Communication Eng. Sungkyunkwan University
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Jun Young‐hyun
Samsung Electronics
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Kong Bai-Sun
School of Inform. and Comm. Eng., Sungkyunkwan University
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