Low-power dual-supply clock networks with clock gating and frequency doubling

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概要

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• Low-power dual-supply clock networks based on novel level-converting clock gating cells are presented. The proposed clock networks achieve a substantial power saving with mitigated timing constraints on gated clocks. They also allow pulse-based flip-flops used at leaf clock nodes to work with no pulse generators, resulting in more power saving and area reduction. The proposed dual-supply clock networks were designed in a 32nm CMOS technology. The evaluation results indicated that the proposed clock-gating cells have up to 24.8% smaller power with 74.3% reduced latency and 17.5% reduced area. They also indicate that the power consumption of the proposed clock networks was reduced by up to 30.3%.

著者

• Han Tae

  School Of Information And Communication Engineering Sungkyunkwan University

• Kong Jeong-taek

  Samsung Electronics Co. Ltd.

• Kong Bai-Sun

  School of Inform. and Comm. Eng., Sungkyunkwan University

• Lee Hoi-Jin

  School of Inform. and Comm. Eng., Sungkyunkwan University

• Kim Jong-Woo

  School of Inform. and Comm. Eng., Sungkyunkwan University

• Son Jae

  SOC Team, System LSI Division, Samsung Electronics

• Kong Jeong-Taek

  Samsung Semiconductor Institute of Technology, Samsung Electronics

• Han Tae

  School of Inform. and Comm. Eng., Sungkyunkwan University

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