Interconnect Modeling in Deep-Submicron Design (Special lssue on SISPAD'99)

概要

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As scaling has been continued more than 20years, it has yielded faster and denser chips with ever increasing functionality. The scaling will continue down to or beyond 0.1μm as proposed in SIA Technical Road map. With scaling, device performance improves, however, interconnect performance is degraded. In this scaled deep submicron technology, however, interconnects limit the perfomance, packing density and yield, if not properly modeled. In order to properly model and design the interconnect-dominated circuits, accurate and proper interconnect modeling is a must to assure the performance and functionality of ever-increasing complex multi-million transistor VLSI circuits. In this paper, the overall flow of interconnect modeling in IC design is reviewed including interconnect characterization, various 2-D/3-D field solvers, 2-D/3-D interconnect model library generation, and parameter extraction. And advanced topics of interconnect modeling in deep submicron are reviewed ; statistical interconnect modeling.
社団法人電子情報通信学会の論文
2000-08-25