New low-voltage small-area mixed-voltage I/O buffer

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概要

• 論文の詳細を見る

• A new mixed-voltage I/O buffer having the characteristics of low-voltage operation and small-area realization is proposed. The proposed I/O buffer provides significantly reduced latency at low supply voltages by eliminating the voltage swing degradation at timing-critical nets. The buffer also provides smaller layout area by avoiding the use of dedicated extra circuits like dynamic gate-bias circuit (DGBC) and hot-carrier prevention circuits (HCPC) to cope with hot-carrier-induced gate-oxide reliability issue. Comparison results in an 80-nm CMOS process indicate that the proposed mixed-voltage I/O buffer achieves 73% reduction on buffer latency, 23% reduction on operating voltage, and 31% reduction on layout area as compared to conventional I/O buffers.

• The Institute of Electronics, Information and Communication Engineersの論文

著者

• Kim Joung-yeal

  School Of Information And Communication Engineering Sungkyunkwan University

• Kong Bai-sun

  School Of Information And Communication Eng. Sungkyunkwan University

• KONG Bai-Sun

  School of Information and Communication Eng., Sungkyunkwan University

• Park Yoon-Suk

  School of Information and Communication Eng., Sungkyunkwan University

• Jun Young-Hyun

  DRAM Design Team, Memory Division, Samsung Electronics

• Kim Joung-Yeal

  School of Information and Communication Eng., Sungkyunkwan Univ.

• Kim Joung-Yeal

  School of Information and Communication Eng., Sungkyunkwan University

• Kong Bai-Sun

  School of Inform. and Comm. Eng., Sungkyunkwan University

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