Novel explicit pulse-based flip-flop for high speed and low power SoCs

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概要

• 論文の詳細を見る

• In this paper, novel explicit pulse-based flip-flop having dual precharge nodes is presented. Dual precharging can minimize the parasitic capacitance of each precharge node by making output transistors driven separately, resulting in high-speed and low-power operation. The switching speed is further improved by avoiding the use of stacked transistors for driving the output load. Pulse-based nature of the proposed flip-flop also provides a negative setup time and minimizes the effects of clock skew. The proposed flip-flop was designed using a 0.18um CMOS technology, whose comparison results indicate that the flip-flop achieves up to 32% power reduction with 11% speed improvement. They also indicate that the power-delay product is decreased by up to 39% compared to conventional pulse-based flip-flops.

• The Institute of Electronics, Information and Communication Engineersの論文

著者

• Kang Sung-chan

  School Of Information And Communication Engineering Sungkyunkwan University

• Kong Bai-Sun

  School of Inform. and Comm. Eng., Sungkyunkwan University

• Jung Byung-Hwa

  School of Information and Communication Engineering, Sungkyunkwan University

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