Effective Fixed-Point Pipelined Divider for Mobile Rendering Processors

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概要

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• In this paper, we proposed that an area- and speed-effective fixed-point pipelined divider be used for reducing the bit-width of a division unit to fit a mobile rendering processor. To decide the bit-width of a division unit, error analysis has been carried out in various ways. As a result, when the original bit-width was 31-bit, the proposed method reduced the bit-width to 24-bitand reduced the area by 42% with a maximum error of 0.00001%.

著者

• Park Woo-chan

  Department Of Computer Science Yonsei University

• Bae Jun-hyun

  Department Of Ceramic Engineering Yonsei University

• Han Tack-don

  Department Of Computer Science Yonsei University

• Park Yong-jin

  Department Of Computer Science And Engineering Graduate School Of Global Information And Telecommuni

• BAE Jun-Hyun

  Department of Computer Science, Engineering College of Yonsei University

• PARK Jinhong

  Department of Computer Science, Engineering College of Yonsei University

• Park Woo-Chan

  Department of Computer Engineering, Sejong University

• PARK Yong-Jin

  Department of Computer Science, Engineering College of Yonsei University

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