Kang Sungho | Department of Electrical & Electronic Engineering, Yonsei University

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概要

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著作論文

A high performance network-on-chip scheme using lossless data compression
MTR-Fill : A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs
An Effective Programmable Memory BIST for Embedded Memory
An Effective Built-In Self-Test for Chargepump PLL(Papers Selected from AP-ASIC 2004)
A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST
A New Low Power Test Pattern Generator for BIST Architecture(Semiconductor Materials and Devices)
A Low-Power Implementation Scheme of Interpolation FIR Filters Using Distributed Arithmetic(Integrated Electronics)
An Acceleration Processor for Data Intensive Scientific Computing(Scientific and Engineering Computing with Applications)(Hardware/Software Support for High Performance Scientific and Engineering Computing)
A Clustered RIN BIST Based on Signal Probabilities of Deterministic Test Sets(Dependable Computing)

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