Noise-Tolerant DAC BIST Scheme Using Integral Calculus Approach

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概要

• 論文の詳細を見る

• This paper proposes a built-in self-test (BIST) scheme for noise-tolerant testing of a digital-to-analogue converter (DAC). The proposed BIST calculates the differences in output voltages between a DAC and test modules. These differences are used as the inputs of an integrator that determines integral nonlinearity (INL). The proposed method has an advantage of random noise cancelation and achieves a higher test accuracy than do the conventional BIST methods. The simulation results show high standard noise-immunity and fault coverage for the proposed method.

• （社）電子情報通信学会の論文
• 2011-08-01

著者

• Kang Sungho

  Yonsei University

• Son Hyeonuk

  Yonsei University

• Ahn Jin-ho

  Hoseo University

• Kim Jeong-do

  Hoseo University

• KIM Incheol

  Yonsei University

• LEE Sang-Goog

  Catholic University

関連論文

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• A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters
• A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST
• A New Analog-to-Digital Converter BIST Considering a Transient Zone(Integrated Electroics)
• Noise-Tolerant DAC BIST Scheme Using Integral Calculus Approach
• Built-In Self-Test for Static ADC Testing with a Triangle-Wave

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