Influence of Soldering Conditions on Void Formation in Large-area Solder Joints

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Impact of High Heating Rate, Low Temperature, and Short Time Annealing on the Realization of Low Resistivity Cu Wire
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Microstructures of 50-nm Cu Interconnects along the Longitudinal Direction
Influence of Grain Size Distributions on the Resistivity of 80nm Wide Cu Interconnects
Aspect ratio dependence of the resistivity of fine line Cu interconnects
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Influence of P Content in Electroless Plated Ni-P Alloy Film on Interfacial Structures and Strength between Sn-Zn Solder and Plated Au/Ni-P Alloy Film
Influence of Phosphorus Concentration in Electroless Plated Ni-P Alloy Film on Interfacial Structures and Strength between Sn-Ag-(-Cu) Solder and Plated Ni-P Alloy Film
Influence of Soldering Conditions on Void Formation in Large-area Solder Joints
The Influence of Phosphorus Concentration of Electroless Plated Ni-P Film on Interfacial Structures in the Joints between Sn-Ag Solder and Ni-P Alloy Film
A Void Free Soldering Process in Large-Area, High Power Insulated Gate Bipolar Transistor Modules
Reliability Enhancement of Solder Joints Made by a Void Free Soldering process
Interface Reaction between Solder and Plated Nickel Film
Studies on Twin Electrode Switching Arc Welding Method (Report 6) : Welding of Copper Plate with Switching TIG-MIG Welding Method
Arc Phenomena and Effects in Switching TIG-MIG Welding Method
Studies on Twin Electrode Switching Arc Welding Method (Report 5) : Arc Phenomena with Switching TIG-MIG Welding Method
Studies on Twin Electrode Switching Arc Welding Method (Report 4) : High Speed Welding of Thin Aluminum Alloy Plate with Twin Electrode Switching TIG
Studies on Twin Electrode Switching Arc Welding Method (Report 3) : Weld Bead Formation for Copper Plate with Twin Electrode Switching TIG
Investigation of Low Loss and High Reliability Encapsulation Technology in Large-Area, High-Power Semiconductor Devices
多結晶銅薄膜の粒成長に及ぼす不純物の影響
Effect of Additive-Free Plating and High Heating Rate Annealing on the Formation of Low Resistivity Fine Cu Wires
A Void Free Soldering Process in Large-Area, High Power Insulated Gate Bipolar Transistor Modules
Void Generation Mechanism in Cu Filling Process by Electroplating for Ultra Fine Wire Trenches
Aspect Ratio Dependence of the Resistivity of Fine Line Cu Interconnects
Filling 80-nm-Wide and High-Aspect-Ratio Trench with Pulse Wave Copper Electroplating and Observation of the Microstructure
Observation of Microstructures in the Longitudinal Direction of Very Narrow Cu Interconnects
Influence of Minimum Barrier Metal Thickness at Trenches on Void Formation in 50-nm-wide Cu Wiring

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