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Renesas Technology Corp. | 論文
- Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
- A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications(Special Issue on High-Performance and Low-Power Microprocessors)
- A New Hierarchical RSM for TCAD-Based Device Design in 0.4μm CMOS Development (Special Issue on Microelectronic Test Structure)
- Analyses on Monolithic InP HEMT Resistive Mixer Operating under Very Low LO Power
- Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
- An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's(Special Issue on the 1994 VLSI Circuits Symposium)
- An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5-V DRAM's (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC(Novel Device Architectures and System Integration Technologies)
- Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh(Memory, Low-Power LSI and Low-Power IP)
- Influence of Cu-Ion Migration and Fine-Line Effect on Time-Dependent Dielectric Breakdown Lifetime of Cu Interconnects
- Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM(Memory Design and Test,VLSI Design and CAD Algorithms)
- Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation(Digital,Low-Power, High-Speed LSIs and Related Technologies)
- Impact of Self-Heating in Wire Interconnection on Timing
- An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
- Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
- Proposal of Metrics for SSTA Accuracy Evaluation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature(Simulation and Verification,VLSI Design and CAD Algorithms)
- On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design(Prediction and Analysis, VLSI Design and CAD Algorithms)
- Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances(Parasitics and Noise)(VLSI Design and CAD Algorithms)
- Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances