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Renesas Technology Corp. | 論文
- Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects
- An Approach for Practical Use of Common-Mode Noise Reduction Technique for In-Vehicle Electronic Equipment
- On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform
- A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI(Memory,Low-Power, High-Speed LSIs and Related Technologies)
- An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design(Novel Device Architectures and System Integration Technologies)
- A 130-nm CMOS 95-mm^2 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput(Integrated Electronics)
- Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation(Interconnect,VLSI Design and CAD Algorithms)
- Wide-Range V_ Controllable SOTB (Silicon on Thin BOX) Integrated with Bulk CMOS Featuring Fully Silicided NiSi Gate Electrode
- Improvement of Device Characteristics Variation by using a Body-Bias Controlling Technology Based on a Hybrid Trench Isolated SOI
- Dihydropyrrolizines from the Male Scent-Producing Organs of a Danaid Butterfly, Ideopsis similis (Lepidoptera: Danaidae) and the Morphology of Alar Scent Organs
- Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories(Memory,Low-Power, High-Speed LSIs and Related Technologies)
- Comprehensive Matching Characterization of Analog CMOS Circuits
- V_/E_-Driven Breakdown of Ultrathin SiON Gate Dielectrics in p-Type Metal Oxide Semiconductor Field Effect Transistors under Low-Voltage Inversion Stress
- Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use(Analog Circuit and Device Technologies)
- Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills(Interconnect, VLSI Design and CAD Algorithms)
- A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills(VLSI Design Technology and CAD)
- Modeling and Simulation on Degradation of Submicron NMOSFET Current Drive due to Velocity-Saturation Effects (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD93))
- Evaluation of Two-Dimensional Transient Enhanced Diffusion of Phosphorus during Shallow Junction Formation (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD93))
- Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis
- A Novel Expression of Spatial Correlation by a Random Curved Surface Model and Its Application to LSI Design