Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM(Memory Design and Test,<Special Section>VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
Instability of SRAM memory cells derived from aggressive technology scaling has been recently one of the most significant issues. Although a 7T-SRAM cell with an area-tolerable separated read port improves read margins even at sub-1V, it unfortunately results in degradation of write margins. In order to assist the write operation, we address a new memory cell employing a look-ahead body-bias which dynamically controls the threshold voltage. Simulation results have shown improvement in both the write margins and access time without increasing the leakage power derived from the body-bias.
- 社団法人電子情報通信学会の論文
- 2007-12-01
著者
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Tada Akira
Renesas Technology Corp.
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NUMA Masahiro
Graduate School of Engineering, Kobe University
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Numa Masahiro
Graduate School Of Science And Technology Kobe University
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Numa Masahiro
Graduate School Of Engineering Kobe University
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Ipposhi Takashi
Renesas Technology Corp.
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Iijima Masaaki
Graduate School Of Science And Technology Kobe University
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Tada A
Renesas Technology Corp.
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SETO Kayoko
Graduate School of Science and Technology, Kobe University
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Seto Kayoko
Graduate School Of Science And Technology Kobe University
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