Application of Error Diagnosis Technique to Incremental Synthesis(Design Methodology)(<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• In an LSI design process, Engineering Change Orders (ECO's) are often given even after the layout process. This letter presents an approach to change the design to satisfy the new specification with ECO's by employing an error diagnosis technique. Our approach performs incremental synthesis using spare cells embedded on the original layout. Experimental results show that applying the error diagnosis technique to incremental synthesis is effective to suppress increase in delay time caused by ECO's.

• 社団法人電子情報通信学会の論文
• 2003-12-01

著者

• YAMAMOTO Keisuke

  Faculty of Pharmaceutical Sciences, Kobe-Gakuin University

• INOUE Hiroshi

  Faculty of Engineering, Himeji Institute of Technology

• Numa Masahiro

  Graduate School Of Science And Technology Kobe University

• Numa Masahiro

  Graduate School Of Engineering Kobe University

• Numa Masahiro

  Faculty Of Engineering Kobe University

• IWASAKI Takahiro

  Faculty of Engineering, Kobe University

• SUGANE Toshifumi

  Faculty of Engineering, Kobe University

• Iwasaki Takahiro

  Faculty Of Engineering Kobe University

• Sugane Toshifumi

  Faculty Of Engineering Kobe University

• Yamamoto Keisuke

  Faculty Of Engineering Kobe University

• Inoue Hiroshi

  Faculty Of Engineering And Resource Science Akita University

• Inoue Hiroshi

  Faculty Of Eng. Osaka Univ.

• Inoue Hiroshi

  Faculty Of Engineering Kobe University

• YAMAMOTO Keisuke

  Faculty of Engineering, Kobe University

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